This invention relates generally to semiconductor processing and, more particularly to a method and apparatus for preventing damage to gate oxide due to ultraviolet radiation associated with semiconductor processes.
In the manufacture of semiconductors, ultraviolet (UV) radiation is encountered during various related processes. For example, UV radiation plays a prominent role during the construction of a gate on a conventional substrate. As shown in Prior Art FIG. 1a, a stack 5 including a silicon layer 10, an oxide layer 12, and a polysilicon layer 14 is etched by first applying a photoresist layer 16 thereon. This photoresist layer 16 is subsequently patterned by being exposed to UV radiation.
During the patterning of the photoresist layer 16, the UV radiation tends to reflect off the polysilicon layer 14. This reflection in turn leads to constructive interference that results in side walls 18 of the patterned photoresist layer 16 becoming non-linear. This non-linearity of the side walls 18 of the patterned photoresist layer 16 is undesirable since it tends to lead to non-uniform etching later. See the detailed view of Prior Art FIG. 1a. 
To combat this problem, a UV absorbing layer 20, i.e. SiON, may be deposited on the polysilicon layer 14 prior to applying the photoresist layer 16. Note Prior Art FIG. 1b. Such UV absorbing layer 20 serves to absorb the UV radiation thus precluding reflection and thereby improving the linearity of the patterning, as shown in the detailed view of Prior Art FIG. 1b. As shown in Prior Art FIG. 1c, with the patterned photoresist layer 16 in place, the stack 5 may be etched to form a gate 22.
Yet another semiconductor process that produces UV radiation is etching. Specifically, UV radiation is an inherent byproduct of plasma that is used during the process of etching. It should be noted that UV radiation generated during etching is undesirable for a reason much different from that associated with patterning photoresist, as mentioned hereinabove. During etching, UV radiation is undesirable due to the adverse affects on the gate oxide layer 12. In particular, UV radiation damages the gate oxide layer 12 to the extent of increasing the probability of device failure in the resulting integrated circuit.
In the past, the remnants of the UV absorbing layer 20 associated with patterning photoresist have been relied upon to protect the gate oxide layer 12 in a manner shown in Prior Art FIG. 1d. It is thus fortuitous that the UV absorbing layer 20, which was required earlier for different reasons, is now useful in absorbing UV radiation that would otherwise damage the gate oxide layer 12. As will become apparent later, however, such UV absorbing layer 20 fails to completely protect the gate oxide layer 12 from the UV radiation.
While the amount of etching-related UV radiation reaching the gate oxide layer has been considered acceptable in the past, this is no longer the case in view of the recent use of thinner gate oxides and high density plasma during the etching process. Associated with such use of high density plasma is greater amounts of UV radiation that in turn inflict more damage on the gate oxide layer 12. This augmented UV radiation has the potential of more easily penetrating the various layers of the stack 5 and causing damage to exposed areas of the gate oxide layer 12.
To put the severity of the present trend in perspective, a historical comparison may be made in relation to gate oxide failure due to other causes. In the past, UV radiation-related device failure has been considered low with respect to device failure due to the gate oxide layer 12 being subject to charging. Accordingly, much time and effort has been contributed to charge damage protection, as oppose to protection against UV radiation. This is due mainly to the contention that standard intermetal oxide (IMO) layers 24 and the aforementioned remnants of the UV absorbing layer 20 offered sufficient protection against UV radiation. For example, given an IMO thickness of 2 xcexcm, only about 38% of surface UV radiation reaches the gate oxide layer 12.
However, studies indicate that failure due to exposure of the gate oxide layer 12 to UV radiation has become increasingly prominent with the emerging use of high density plasmas. As shown in Prior Art FIG. 1e, it is shown that optical emissions spectrometer (OES) intensity associated with high density plasma peaks at wavelengths in the UV range. It has been shown that UV radiation associated with such high density plasma has been sufficient to overcome the protection afforded by standard IMO layer 24 and the UV absorbing layer 20 to bring rise to increased device failure.
This problem is compounded by the fact that the gate oxide layer 12 is exposed, and therefore more susceptible to UV radiation at edges 26 of the gate 22. UV radiation from high density plasma can thus reach the edges 26 of the gate oxide layer 12 with greater ease.
This increase in device failure caused by UV radiation has thus become comparable to the previously dominant charge-related device failure. Prior Art FIG. 1f depicts this relationship between the affects of UV radiation and charging on gate oxide layer 12. As shown, effects of UV radiation are increasingly important and even become the dominating factor in processes dealing with leading edge technology, i.e. ≈0.1 xcexcm.
To address this emerging trend, various methods have been established to combat the negative effects of UV radiation on gate oxides. Prior Art FIG. 1g shows a cross-sectional view of a gate 22 with IMO layer 24 thereon. In addition to such conventional structure, a UV absorbing layer 30 is disposed on top of the IMO layer 24. In such position, the UV absorbing layer 30 may be better suited to prevent damage to the gate oxide layer 12. As shown in Prior Art FIG. 1g, however, UV radiation is still permitted to access the gate oxide layer 12 and therefore damage the gate oxide layer 12, especially after etching is carried out.
There is thus a need for a method and apparatus for further preventing damage to a gate oxide layer of a semiconductor stack that results from UV radiation associated with semiconductor plasma etching, wherein such protection is afforded particularly in the proximity of the edges of the gate oxide layers.
As set forth hereinabove, protection against UV radiation may be afforded by the incorporation of a UV-absorbing material on top of the IMO layer. Such material is known to take the form of SiN or SiON. While partially effective, stoichiometric SiN and SiON still leave much to desire in terms of protection of gate oxides against UV radiation.
There is thus a need for a material that prevents UV radiation-related damage to a gate oxide layer of a semiconductor stack in a more effective manner.
A system and apparatus is provided for preventing damage to gate oxide due to ultraviolet (UV) radiation associated with semiconductor processes. Included is a substrate and a gate formed on the substrate. The gate includes a gate material layer and a gate oxide layer positioned on the substrate. A pair of spacers are situated on opposite sides of the gate. Deposited over the gate and the spacers is a UV radiation blocking material for preventing the UV radiation from damaging the gate oxide layer of the gate. Finally, at least one metal and intermetal oxide layer is positioned over the UV radiation blocking material.
In another embodiment, instead of the UV blocking material being deposited over the gate and the spacers, the spacers are constructed from the UV radiation blocking material for preventing the UV radiation from damaging the gate oxide layer of the gate. In such embodiment, the UV radiation blocking material serves as both an insulating layer between the gate and upper layers of the semiconductor stack, and further protects the gate oxides against UV radiation associated with plasma etching.
Yet another embodiment of the present invention addresses the need for additional materials to use as protection against damage to gate oxides during semiconductor processes. In particular, the present invention offers a plurality of materials which more effectively protect gate oxides against UV radiation associated with semiconductor processes.
These and other advantages of the present invention will become apparent upon reading the following detailed description and studying the various figures of the drawings.